此规则是错误的:

$(OBJECTS): $(SOURCES) makefile

这将扩展为什么?如果您有来源 src/foo.cpp ， src/bar.cpp 和 src/baz.cpp ，那么它将是:

What does this expand to? If you have sources src/foo.cpp, src/bar.cpp, and src/baz.cpp then it will be this:

obj/foo.o obj/bar.o obj/baz.o : src/foo.cpp src/bar.cpp src/baz.cpp makefile

这是一个非常普遍的问题:人们似乎有一个想法，make将以某种方式按摩所有这些目标和先决条件以某种方式匹配它们，以便每个目标文件仅依赖于相应的源文件.

This is an extremely common problem: people seem to have this idea that make will somehow massage all these targets and prerequisites to match them up somehow so that each object file depends only on the corresponding source file.

但是，make不会那样做.上面的规则与编写所有这些规则完全相同:

But, make does NOT do that. The above rule is exactly identical to writing all these rules:

obj/foo.o : src/foo.cpp src/bar.cpp src/baz.cpp makefile
obj/bar.o : src/foo.cpp src/bar.cpp src/baz.cpp makefile
obj/baz.o : src/foo.cpp src/bar.cpp src/baz.cpp makefile

现在也许您可以看到为什么会看到自己的行为:每个目标的第一个前提条件是完全相同的文件 src/foo.cpp ，因此，当您使用 $<自动变量，这就是您总是得到的.

Now maybe you can see why you see the behavior you do: the first prerequisite for every target is exactly the same file src/foo.cpp so when you use the $< automatic variable, that's the one you always get.

您必须编写一个构建一个对象的规则，然后让我们弄清楚如何将该规则应用于所有适当的对象.

You have to write ONE rule that builds ONE object, then let make figure out how to apply that rule for all the appropriate objects.

因此，要从一个源文件构建一个目标文件，可以使用如下模式规则:

So, to build one object file from one source file you can use a pattern rule like this:

obj/%.o : src/%.cpp makefile
        @mkdir -p obj
        $(CXX) $(WARNING) $(CXXFLAGS) -MMD -MP -c $< -o $@

这就是您所需要的.