缓存的思想是以1个周期交付缓存的数据，以保持CPU以最大速度运行。

The idea of a cache is to deliver cached data in 1 cycle to keep the CPU running at maximum speed.

现在，所有CPU均已流水线化。这意味着它们具有独立的模块，例如获取一条指令，对其进行解码，获取操作数，执行该指令，然后回写结果。对于所有不同的指令，所有这些流水线阶段均尽可能在同一时间执行。

为了获得最大速度，必须与之前解码的较早指令的操作数获取同时进行指令获取。如果一个人具有一条指令高速缓存和一个数据高速缓存，则只能在1个周期内同时（在***情况下）完成这两者。

Now today all CPUs are pipelined. This means the they have independent modules that e.g. fetch an instruction, decode it, fetch the operands, execute the instruction, and write back the result. All of these pipeline stages are executed whenever possible at the same time for different instructions.
For maximum speed, an instruction fetch has to be done at the same time as an operand fetch of an earlier instruction decoded before. Both can only be done (in the optimal case) at the same time in 1 cycle if one has an instruction cache and a data cache.