我确定99％的主要因素是晶体管的实现成本.显然这将非常有用，并且不存在的唯一原因是实施成本必须超过重大收益.

不太可能出现编码空间问题； VEX编码空间提供了很多空间.实际上，由于代表前缀组合的字段不是位字段，因此它是一个整数，其中大部分值未使用.

尽管如此，他们决定为AVX512VBMI实现它，并且在AVX512BW和AVX512F中提供更大的元素尺寸.也许他们意识到没有这个很烂，于是决定还是这么做. AVX512F需要大量的裸片面积/晶体管来实现，以至于英特尔决定甚至不在零售台式机CPU中实现它 vpermi2b ，它可以从128B表中进行64个并行表查找( 2个zmm向量)). Skylake Xeon仅会带来vpermi2w和更大的元素尺寸(AVX512F + AVX512BW).

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我非常确定，即使8:1混合器的宽度是4倍，我也相信32个32:1混合器的价格要比八个8:1混合器贵得多.他们可以通过多个阶段的改组(而不是单个32:1阶段)来实现它，因为跨车道改组需要3个周期的时间预算才能完成工作.但是仍然有很多晶体管.

我很想看到有硬件设计经验的人的建议.我曾经在面包板上用TTL计数器芯片构建了一个数字计时器(然后IIRC在TI-99/4A上从BASIC读出了计数器，即使在20年前也已经过时了)，但是仅此而已.

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很明显，SSE PSHUFB 指令几乎是有史以来最有用的指令之一.

是的.这是第一个变量改组，带有来自寄存器而不是立即数的控制掩码.根据pcmpeqb/pmovmskb结果从LUT随机掩码中查找随机掩码可以做一些疯狂的强大事情. @stgatilov的IPv4点分四进制->整数转换器是我最喜欢的SIMD绝妙技巧之一.

AVX2 has lots of good stuff. For example, it has plenty of instructions which are pretty much strictly more powerful than their precursors. Take VPERMD: it allows you to totally arbitrarily broadcast/shuffle/permute from one 256-bit long vector of 32-bit values into another, with the permutation selectable at runtime¹. Functionally, that obsoletes a whole slew of existing old unpack, broadcast, permute, shuffle and shift instructions³.

Cool beans.

So where is VPERMB? I.e., the same instruction, but working on byte-sized elements. Or, for that matter, where is VPERMW, for 16-bit elements? Having dabbled in x86 assembly for some time, it is pretty clear that the SSE PSHUFB instruction is pretty much among the most useful instructions of all time. It can do any possible permutation, broadcast or byte-wise shuffle. Furthermore, it can also be used to do 16 parallel 4-bit -> 8-bit table lookups².

Unfortunately, PSHUFB wasn't extended to be cross-lane in AVX2, so it is restricted to within-lane behavior. The VPERM instructions are able to do cross shuffle (in fact, "perm" and "shuf" seem to be synonyms in the instruction mnemonics?) - but the 8 and 16-bit versions were omitted?

There doesn't even seem to be a good way to emulate this instruction, whereas you can easily emulate the larger-width shuffles with smaller-width ones (often, it's even free: you just need a different mask).

I have no doubt that Intel is aware of the wide and heavy use of PSHUFB, so the question naturally arises as to why the byte variant was omitted in AVX2. Is the operation intrinsically harder to implement in hardware? Are there encoding restrictions forcing its omission?

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¹By selectable at runtime, I mean that the mask that defines the shuffling behavior comes from a register. This makes the instruction an order of magnitude more flexible than the earlier variants that take an immediate shuffle mask, in the same way that add is more flexible than inc or a variable shift is more flexible than an immediate shift.

²Or 32 such lookups in AVX2.

³The older instructions are occasionally useful if they have a shorter encoding, or avoid loading a mask from memory, but functionally they are superseded.

I'm 99% sure the main factor is transistor cost of implementation. It would clearly be very useful, and the only reason it doesn't exist is that the implementation cost must outweigh the significant benefit.

Coding space issues are unlikely; the VEX coding space provides a LOT of room. Like, really a lot, since the field that represents combinations of prefixes isn't a bit-field, it's an integer with most of the values unused.

They decided to implement it for AVX512VBMI, though, with larger element sizes available in AVX512BW and AVX512F. Maybe they realized how much it sucked to not have this, and decided to do it anyway. AVX512F takes a lot of die area / transistors to implement, so much that Intel decided not to even implement it in retail desktop CPUs for a couple generations.

(Part of that is that I think these days a lot of code that can take advantage of brand new instruction sets is written to run on known servers, instead of runtime dispatching for use on client machines).

According to Wikipedia, AVX512VBMI isn't coming until Cannonlake, but then we will have vpermi2b, which does 64 parallel table lookups from a 128B table (2 zmm vectors)). Skylake Xeon will only bring vpermi2w and larger element sizes (AVX512F + AVX512BW).

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I'm pretty sure that thirty two 32:1 muxers are a lot more expensive than eight 8:1 muxers, even if the 8:1 muxers are 4x wider. They could implement it with multiple stages of shuffling (rather than a single 32:1 stage), since lane-crossing shuffles get a 3-cycle time budget to get their work done. But still a lot of transistors.

I'd love to see a less hand-wavy answer from someone with hardware design experience. I built a digital timer from TTL counter chips on a breadboard once (and IIRC, read out the counter from BASIC on a TI-99/4A which was very obsolete even ~20 years ago whe), but that's about it.

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It's pretty clear that the SSE PSHUFB instruction is pretty much among the most useful instructions of all time.

Yup. It was the first variable-shuffle, with a control mask from a register instead of an immediate. Looking up a shuffle mask from a LUT of shuffle masks based on a pcmpeqb / pmovmskb result can do some crazy powerful things. @stgatilov's IPv4 dotted-quad -> int converter is one of my favourite examples of awesome SIMD tricks.