是的，你可以，我认为这是***实践 - 它意味着最少的工作、***的理解、最简单的维护和最简洁的设计.

Yes you can, and I regard it as best practice - it means least work, best understanding, easiest maintenance, and cleanest design.

诀窍是在包中声明整个设计通用的类型(我通常称其为通用":-)，并在实体声明之前添加 use work.Common.all 并在该实体的每个客户.当然，更专业的组件可以有适当的名称！

The trick is to declare the types common to your whole design in a package (I usually call it "Common" :-) and add use work.Common.all before the entity declaration AND in every customer of that entity. More specialised components can have appropriate names, of course!

例如:

package Common is    -- untested...

   type my_enum_type is (r1, r2, r3);

   -- (optional) useful tools
   function to_slv (e : my_enum_type) return std_logic_vector;
   function to_enum (s : std_logic_vector(my_enum'length downto 0)) 
                    return my_enum_type;

end Common;

package body Common is
   -- subprogram bodies here
end Common;

现在，当您向枚举添加值时，您只需修改Common"并重建设计，而那些遵循传统准则的人仍在尝试识别每个端口和信号，他们必须增加std_logic_vector"的范围" 1.

Now when you add a value to the enumeration, you ONLY modify "Common" and rebuild the design, while those who follow conventional guidelines are still trying to identify every port and signal where they have to increase the range of their "std_logic_vector" by 1.

对于总线接口也非常有效，其中每个方向的记录都隐藏了所有单独的总线和握手信号.

Works really well for bus interfaces too, where a record in each direction hides all the individual bus and handshaking signals.

您将不得不与 Xilinx自动测试台生成器"等脑残工具作斗争，这些工具将有助于将您的所有端口类型(整数或布尔值以及自定义)转换为 std_logic(_vector)，然后无法编译.只需将它们重新翻译回来即可.

You WILL have to fight brain-dead tools like Xilinx "automatic testbench generator" which will helpfully translate ALL your port types - integer or boolean as well as custom - into std_logic(_vector) and then fail to compile. Just translate them back again.

您仍然可以假设在最顶层，所有外部 FPGA 引脚仍应基于 std_logic.如果您需要模拟设计的综合后版本，那么您要么需要使用 std_logic_vector 端口，要么添加一个简单的包装器以从一种形式转换为另一种形式.

You can still make a case that at the very top level, all the external FPGA pins should still be std_logic based. And if you ever need to simulate a post-synthesis version of your design, then you will either need to live with std_logic_vector ports, or add a simple wrapper to convert from one form to the other.